1 1 1/12/01 supertex inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." supertex does not assume responsibility for use of devices described and limits its liabi lity to the replacement of devices determined to be defective due to workmanship. no responsibility is assumed for possible omissions or inaccuracies. circuitry and specifications are subject to c hange without notice. for the latest product specifications, refer to the supertex website: http://www.supertex.com. for complete liability information on all supertex products, refer to the most curre nt databook or to the legal/disclaimer page on the supertex website. VN0606 advanced dmos technology these enhancement-mode (normally-off) transistors utilize a vertical dmos structure and supertex? well-proven silicon-gate manufacturing process. this combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inher- ent in mos devices. characteristic of all mos structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. supertex? vertical dmos fets are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. ordering information order number / package bv dss /r ds(on) i d(on) bv dgs (max) (min) to-92 60v 3.0 ? 1.5a VN0606l features ? free from secondary breakdown ? low power drive requirement ? ease of paralleling ? low c iss and fast switching speeds ? excellent thermal stability ? integral source-drain diode ? high input impedance and high gain ? complementary n- and p-channel devices applications ? motor controls ? converters ? amplifiers ? switches ? power supply circuits ? drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.) absolute maximum ratings drain-to-source voltage bv dss drain-to-gate voltage bv dgs gate-to-source voltage 30v operating and storage temperature -55 c to +150 c soldering temperature* 300 c * distance of 1.6 mm from case for 10 seconds. package option note: see package outline section for dimensions. n-channel enhancement-mode v ertical dmos fets t o-92 s g d
2 1235 bordeaux drive, sunnyvale, ca 94089 tel: (408) 744-0100 ?fax: (408) 222-4895 www.supertex.com 1 1/12/01 ?001 supertex inc. all rights reserved. unauthorized use or reproduction prohibited. symbol parameter min typ max unit conditions bv dss drain-to-source 60 v v gs = 0v, i d = 10 a breakdown voltage v gs(th) gate threshold voltage 0.8 2.0 v i gss gate body leakage 100 na v gs = 30v, v ds = 0v i dss zero gate voltage drain current 10 av gs = 0v, v ds = 50v 500 v gs = 0v, v ds = 50v, t a = 125 c i d(on) on-state drain current 1.5 a v gs = 10v, v ds = 10v r ds(on) static drain-to-source 3.0 ? v gs = 10v, i d = 1a on-state resistance g fs forward transconductance 170 m v ds = 10v, i d = 0.5a c iss input capacitance 50 c oss common source output capacitance 25 pf v gs = 0v, v ds = 25v f = 1 mhz c rss reverse transfer capacitance 5 t (on) turn-on time 10 v dd = 25v, i d = 0.6a, ns r gen = 25 ? t (off) turn-off time 10 v sd diode forward voltage drop 0.85 v v gs = 0v, i sd = 0.47a notes: 1. all d.c. parameters 100% tested at 25 c unless otherwise stated. (pulse test: 300 s pulse, 2% duty cycle.) 2. all a.c. parameters sample tested. thermal characteristics VN0606 electrical characteristics (@ 25 c unless otherwise specified) switching waveforms and test circuit 90% 10% 90% 90% 10% 10% pulse generator v dd r l output d.u.t. t (on) t d(on) t (off) t d(off) t f t r input input output 10v v dd r gen 0v 0v ? package i d (continuous)* i d (pulsed) power dissipation jc ja i dr *i drm @ t c = 25 c c/w c/w to-92 0.33a 1.6a 1w 125 170 0.33a 1.6a * i d (continuous) is limited by max rated t j .
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